The invention relates to digital signaling and more particularly to high frequency preemphasis of a digital signal.
In many digital systems, the interconnection bandwidth between chips is a critical limitation on performance. Historically, intra-chip signaling has performed much more slowly than on-chip processing. As technology continues to scale smaller, this bottleneck will become even more pronounced. Without improvements to high speed digital signaling techniques, interchip signaling will prove to be a limit to the technology.
An example of an ideal digital signal 10 is shown in FIG. 1a. A midpoint 12 is shown that serves to define the change in the value of the data bit. In the lower region 10, the data bit has a value of xe2x80x9c0xe2x80x9d. While in the upper region 14, the data bit has a value of xe2x80x9c1xe2x80x9d. This type of digital scheme with a mid-point 12 is referred to as a single-end signal design. FIG. 1b shows a more realistic view of the waveform of the same digital signal 18. The midpoint 12 as well as we the upper 14 and lower 16 regions are the same. However, the signals are subjected to some suppression of the signal""s peak value called attenuation. The attenuation is particularly pronounced in the case of a single xe2x80x9c1xe2x80x9d in a field of xe2x80x9c0xe2x80x9ds. In some instances, the attenuated signal barely reaches the midpoint 12 which results in a very low probability of detection. The attenuation is primarily caused by skin-effect resistance and dielectric absorption by the transmission line. However, the skin-effect resistance is usually the dominant factor. In any case, the magnitude of the attenuation will increase with the frequency.
With a typical broadband signal, the superposition of an unattenuated low frequency signal component with attenuated high frequency signal components causes intersymbol interference that reduces the maximum frequency at which the system can operate. During this intersymbol interference, or hysteresis, the signal xe2x80x9cremembersxe2x80x9d its previous state. The problem is not so much the magnitude of the attenuation as it is the interference caused by the frequency dependent nature of the attenuation. The interference comes from noise sources such as receiver offset, receiver sensitivity, crosstalk, reflections of previous data bits, and coupled supply noise.
The effects of such interference are shown in FIGS. 2a and 2b. Both of these FIGS. show a differential digital signal design. The differential signal differs from the single end signal in that it provides complementary high and low signals instead of a single signal. FIG. 2a shows an attenuated differential signal 20. The high signal component 22 and the low signal component 24 intersect to form an eye 26. The amplitude of the eye 28 is obviously dependent on the amount of attenuation of each signal. Only a few decibels (dB) of frequency dependent attenuation can be tolerated by such a signaling system before intersymbol interference overwhelms the signal. FIG. 2b shows a differential signal with deterministic jitter 30. The amount of offset 32 of jitter affects the width of the eye and may possibly eliminate the eye entirely as shown in FIG. 2b. Jitter is caused by fluctuations in the sampling clock, fluctuations in the receiving clock, and delay variations in the signal path. Each of these sources of jitter are primarily the result of power supply modulation and crosstalk induced delay variation.
One solution to the problem of intersymbol interference is equalization of the signal by pre-emphasizing the high-frequency components of the signal before transmission. This will blue effectively eliminate the interference. The effects of equalization are shown in FIGS. 3a and 3b. FIG. 3a shows an unequalized signal that is similar to that shown in FIG. 2a. As shown previously, the amplitude 28 of the eye 26 of the signal is reduced due to the frequency dependent attenuation. FIG. 3b shows a signal 36 where both the high signal component 22 and the low signal component 24 have been equalized. As can be clearly seen, the amplitude 40 of the eye 38 is increased while the full width of the eye 38 is maintained.
Equalization is performed by having a main transmitter and an equalizing duplicate transmitter sum their output currents. The equalizing duplicate transmitter operates with a data bit that is delayed by one clock cycle. A prior art embodiment of a high frequency pre-emphasis circuit is shown in FIG. 4. An initial data bit 46 (DN) is provided as an input to a standard xe2x80x9cflip-flopxe2x80x9d circuit 44a. The flip-flop will output the initial data bit (DN) and its complement data bit (DNxe2x80x2) upon receiving a clock pulse 48 whereupon a new initial data bit will be provided to the flip-flop 44a. Both outputs 50 and 52 are then input into a predriver 54. Upon receipt of the clock pulse 48, the output data bit 50 (DNxe2x88x921) is also input into another flip-flop circuit 44b. Because this bit is effectively delayed one clock cycle from being input into the second flip flop 44b, it is the previous data bit 50 (DNxe2x88x921) from the initial data bit 46 (DN). As with the first flip-flop 44a, the second flip-flop 44b will output the previous data bit 50 (DNxe2x88x921) and the complement previous data bit 52 (DNxe2x88x921xe2x80x2) upon receiving a clock pulse 48 into a second predriver 55. The outputs of both flip-flops 44a and 44b are input into two separate predrivers 54 and 55 which each comprise a pass gate multiplexer and a clamping buffer. The output from the predriver 54 for the first flip-flop 44a is input into a 10 mnA output stage 56 while the output from the predriver 55 for the second flip-flop 44b is input into a 10/4 mA output stage 58. The outputs from both output stages 56 and 58 are then combined in the output lines 60.
In one embodiment, the invention is a method for pre-emphasizing a digital signal comprising: receiving a data bit as input for a first flip-flop circuit; outputting the data bit and the complement of the data bit from the first flip-flop circuit; receiving a previous data bit from the output of the first flip-flop circuit as input for a second flip-flop circuit; outputting the previous data bit and the complement of the previous data bit from the second flip-flop circuit; receiving the data bit, the complement of the data bit, the previous data bit, and the complement of the previous data bit as input for a predriver; pre-emphasizing a transition in value between the data bit and the previous data bit with the predriver; and outputting an equalized digital signal from the predriver.
The advantages of the disclosed invention may include the use of single drive stage for pre-emphasizing a high frequency signal. This allows for a reduction of power dissipation, a reduction in required area on the chip, and an increase in the bandwidth.